1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an input buffer.
2. Description of the Related Art
The voltage of signals input to a semiconductor memory device are specified by signal standards such as Stub Series Terminated Logic (SSTL), Low Voltage Transistor-Transistor Logic (LVTTL), and Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS). For example, an interface for LVTTL or LVCMOS signals employs an input buffer having a CMOS inverter circuit with a full-swing amplitude corresponding to an operation voltage of the semiconductor device. Meanwhile, an interface for SSTL signals employs an input buffer using a differential amplifier circuit with a small swing amplitude from a reference voltage, which is a center voltage of the operation voltage. Therefore, in mass production, the two types of input buffers are formed to apply to various interfaces and one of the two is selected by a predetermined metal option.
FIG. 1 is a circuit diagram of a prior art input buffer for converting an input signal of a LVTTL standard into an internal CMOS signal. Referring to FIG. 1, an input buffer 100 includes a CMOS inverter circuit, which receives an input signal IN and generates an output signal OUT. The input buffer 100 uses an external supply voltage VDD or an internal supply voltage IVC as a power source, and generates a stable output signal OUT through an inverter. The inverter outputs a signal of a logic high or low level according to the supply voltage only when a voltage signal IN within a predetermined voltage range less than the supply voltage is received.
In a semiconductor memory device, the input voltage signal IN generally has the same voltage as a data output supply voltage VDDQ. If the data output supply voltage VDDQ is changed over a wide range with respect to the external supply voltage VDD or the internal supply voltage IVC, the input buffer 100, which uses the fixed external supply voltage VDD or internal supply voltage IVC as its power source, cannot accurately determine the voltage of an input signal IN exceeding the fixed supply voltage VDD or IVC.
As mentioned above, the input buffer for converting SSTL signals includes a differential amplifier circuit that compares an input signal with a reference voltage and determines the logic level of the input signal according to the difference between the input signal and the reference voltage, to thereby generate an output signal. The reference voltage is generally fixed at a center voltage between the fixed external supply voltage and ground. However, if the reference voltage is fixed based on the external supply voltage, determination of the logic level of the input signal may be inaccurate and the transition speed of the output signal from a low level to a high level differs from the transition speed of the input signal, causing signal skew.